Senior ISP Engineer

Purpose of the Job: To lead the camera bring-up and integration flow from MIPI CSI through the ISP into system memory, ensuring stable and optimized camera functionality. The role will collaborate with system architects and algorithm engineers to implement, validate, and maintain required camera modes, formats, and timing in accordance with OEM requirements.Responsibilities and Duties:Bring up and maintain MIPI CSI-2 receive paths, sensor drivers, and ISP programming for multiple sensor modes (resolution, frame rate, exposure/gain, HDR variants as applicable). Define and document per-mode data contracts: output format (RAW/YUV/RGB), stride/alignment, bytes per frame, latency and throughput budgets, and mode-switch behavior. Implement ISP control software: initialization tables, dynamic updates (exposure, gain, white balance, flicker mitigation as required), error IRQ handling, and back-pressure behavior when consumers stall. Work with DMA, memory carve-outs, and cache attributes so ISP outputs land in buffers that are safe for CPU and accelerator consumers; avoid implicit copies on the hot path. Collaborate on multicore integration: frame metadata, timebase/frame IDs, and clear ownership of FSYNC / external trigger if used. Build measurement and diagnostics: frame time, drop counts, ISP error counters, structured logging, and reproducible lab capture procedures for debug. Support validation: fault scenarios (sensor disconnect, CSI errors, ISP timeouts), degraded modes, and regression tests aligned with program quality gates. Education:Bachelor’s degree in Computer Engineering, Electrical Engineering, Computer Science, or equivalent experience. Experience:Strong embedded C (or C++) for bare-metal or RTOS environments; comfort with interrupt-driven drivers and real-time constraints. Hands-on experience with camera pipelines: MIPI CSI-2, sensor configuration (I2C/SPI), frame sync, and at least one ISP (on-SoC or companion) in a shipping or advanced development program. Practical knowledge of image formats, color pipelines (e.g. RAW through demosaic/tone/color stages at a systems level), and tuning collaboration with imaging or tuning specialists. Familiarity with DMA, memory alignment, and debugging memory coherency issues between peripherals and CPUs. Experience with an RTOS including thread priorities, ISRs, and avoiding priority inversion on shared resources. Ability to read SoC reference manuals and translate hardware capabilities into stable software interfaces and documentation. Clear written communication: interface specs, integration manuals, and test reports for cross-functional partners. Skills and Abilities: Compilers / debug: ARM GCC or LLVM, GDB or vendor debug with JTAG/SWD (e.g. J-Link, Lauterbach, or vendor-equivalent). OS configuration and integration with vendor SoC SDK. CI mindset: reproducible builds, static analysis participation, and hardware-in-the-loop regression where available. Preferred Qualifications: ● Automotive or functional safety exposure (ISO 26262 concepts, ASIL-aware partitioning, traceability), even if not in a certifying role. Multicore experience (AMP/SMP), inter-processor communication, and shared-memory protocols with versioning. Performance profiling on ARM Cortex-A (cycle counts, cache effects. Experience with hardware lab bring-up: scopes/logic analyzers for MIPI/FSYNC, power sequencing, and systematic fault injection. Exposure to Yocto/Linux is optional.